1. Field of the Invention
The present invention generally relates to systems and methods for creating inspection recipes. Certain embodiments relate to a computer-implemented method for creating an inspection recipe based on a design different from that for which the inspection recipe is being created.
2. Description of the Related Art
The following description and examples are not admitted to be prior art by virtue of their inclusion in this section.
An integrated circuit (IC) design may be developed using a method or system such as electronic design automation (EDA), computer aided design (CAD), and other IC design software. Such methods and systems may be used to generate a circuit pattern database from the IC design. The circuit pattern database includes data representing a plurality of layouts for various layers of the IC. Data in the circuit pattern database may be used to determine layouts for a plurality of reticles. A layout of a reticle generally includes a plurality of polygons that define features in a pattern on the reticle. Each reticle is used to fabricate one of the various layers of the IC. The layers of the IC may include, for example, a junction pattern in a semiconductor substrate, a gate dielectric pattern, a gate electrode pattern, a contact pattern in an interlevel dielectric, and an interconnect pattern on a metallization layer.
The term “design data” as used herein generally refers to the physical design (layout) of an IC and data derived from the physical design through complex simulation or simple geometric and Boolean operations.
A semiconductor device design is verified by different procedures before production of ICs. For example, the semiconductor device design is checked by software simulation to verify that all features will be printed correctly after lithography in manufacturing. Such checking commonly includes steps such as design rule checking (DRC), optical rule checking (ORC), and more sophisticated software-based verification approaches that include process simulation calibrated to a specific fab and process. The output of the physical design verification steps can be used to identify a potentially large number of critical points, sometimes referred to as “hot spots,” in the design.
Fabricating semiconductor devices such as logic and memory devices typically includes processing a substrate such as a semiconductor wafer using a large number of semiconductor fabrication processes to form various features and multiple levels of the semiconductor devices. For example, lithography is a semiconductor fabrication process that involves transferring a pattern from a reticle to a resist arranged on a semiconductor wafer. Additional examples of semiconductor fabrication processes include, but are not limited to, chemical-mechanical polishing (CMP), etch, deposition, and ion implantation. Multiple semiconductor devices may be fabricated in an arrangement on a single semiconductor wafer and then separated into individual semiconductor devices.
Inspection processes are used at various steps during a semiconductor manufacturing process to detect defects on wafers to promote higher yield in the manufacturing process and thus higher profits. Inspection has always been an important part of fabricating semiconductor devices such as ICs. However, as the dimensions of semiconductor devices decrease, inspection becomes even more important to the successful manufacture of acceptable semiconductor devices because smaller defects can cause the devices to fail. For instance, as the dimensions of semiconductor devices decrease, detection of defects of decreasing size has become necessary since even relatively small defects may cause unwanted aberrations in the semiconductor devices.
As design rules shrink, however, semiconductor manufacturing processes may be operating closer to the limitations on the performance capability of the processes. In addition, smaller defects can have an impact on the electrical parameters of the device as the design rules shrink, which drives more sensitive inspections. Therefore, as design rules shrink, the population of potentially yield relevant defects detected by inspection grows dramatically, and the population of nuisance defects detected by inspection also increases dramatically. Therefore, more and more defects may be detected on the wafers, and correcting the processes to eliminate all of the defects may be difficult and expensive.
Some methods involve aligning inspection care areas (e.g., the areas of the device pattern formed on the wafer in which inspection will be performed) to the physical location of the pattern printed on the wafer. However, currently, the care areas can be aligned to the pattern printed on the wafer with an accuracy of no better than about 2 μm due to system errors and imperfections. For instance, some bright field (BF) inspection systems have coordinate accuracies of about +/−1 μm. In addition, the inspection care areas in currently used methods are relatively large and include many noncritical features as well as desired critical features. In trying to maximize the sensitivity of the inspection system to capture subtle spatially systematic “design-for-manufacturability” (DFM) defects resulting from design and process interdependencies, the system may be overwhelmed by millions of events in non-critical areas such as CMP fill regions. Detecting such nuisance defects is disadvantageous for a number of reasons. For example, these nuisance events need to be filtered out of the inspection results by post-processing of the inspection data. In addition, nuisance event detection limits the ultimate achievable sensitivity of the inspection system for DFM applications. A high rate of nuisance defect data may also overload the run time data processing capacity of the inspection system thereby reducing throughput and/or causing the loss of data.
Many current methods of generating an inspection recipe make no use of the design data associated with a device (chip). Recipe generation includes a trial-and-error iterative approach in which the wafer is scanned in different imaging modes and for each such scan, the detection thresholds are varied and defects manually reviewed (usually on a scanning electron microscope (SEM) review station). The die is segmented into regions in a relatively broad sense (e.g., array versus logic), and the thresholds are modified (iteratively) until defects of interest are caught without detecting too many nuisance defects.
The existing methods for inspection recipe setup have a number of disadvantages. For instance, no use is made of design context in these methods. Thus, the partitioning of the die into various regions that are to be inspected with different sensitivities is performed in an ad hoe manner and can vary from operator to operator. In addition, the die partitioning process and threshold selection process is time consuming and must be repeated for each new device. There is no capability of transferring information learned from one device to the next. Furthermore, if the inspection system has many imaging modes, the operator must try each mode (or some sample set of the modes from prior experience) and use a trial-and-error method, varying detection thresholds for each mode, reviewing defects, and then deciding on the best mode to use for subsequent inspections of that device and layer.
Accordingly, it would be advantageous to develop methods and systems for creating inspection recipes that do not have one or more of the disadvantages of the methods and systems described above.